The present invention relates generally to failure analysis and qualification testing of integrated circuits (ICs), and specifically to an apparatus and method for analyzing and visualizing functional failures in an IC. These functional failures result from timing errors in the IC which lead to errors in output states of the IC. The apparatus and method of the present invention can be used to locate any circuit elements in the IC that are responsible for producing functional failures therein.
Functional failures in an integrated circuit (IC) can arise when information traveling along a particular path in the IC (termed herein a critical timing path) is advanced or delayed relative to information traveling along other paths in the IC so that an incorrect value of an output state (i.e. an output voltage) from the IC is produced. Functional failures can be produced by various types of circuit elements including resistive interconnections and switching transistors. An increased resistance in a resistive interconnection can slow down the flow of electricity through that interconnection. Similarly, a delay in a switching transition of a transistor can slow down the flow of an electrical signal being transmitted through that transistor.
The delay in information travel produced by critical timing paths or resistive interconnections is frequency dependent so that over a certain range of clock frequencies, the IC behaves as expected in response to a set of input test vectors since for this range of frequencies the timing error can be accommodated by the IC. However, at higher clock frequencies, the IC can produce an abnormal or inconsistent output in response to the same set of input test vectors. The presence of functional failures in an IC can thus limit the range of clock frequencies over which the IC can be used. Similarly, functional failures can appear in an IC when the IC is operated at a temperature that is too high or too low, or when the operating voltage to the IC is outside a certain range.
An ability to locate any circuit elements which produce or contribute to functional failures is of value since this allows a particular IC to be optimized for speed and accuracy by designing the IC and/or the IC fabrication processes so as to eliminate or minimize critical timing paths or resistive interconnections in the IC, thereby minimizing timing errors in the IC. This can result in an increase in the speed at which the IC can be operated and validated as being free from functional failures. From an economic standpoint, ICs (e.g. computer chips) validated for operation at higher-speeds are of greater value and can gain more market share than lower-speed ICs. Additionally, an ability to locate the circuit elements responsible for producing functional failures in an IC is important for quality control during IC fabrication, for failure analysis of ICs, and for qualification and acceptance testing of ICs.
Heretofore, the analysis of functional failures in ICs has been difficult and time consuming. One method for characterizing critical timing paths and analyzing timing related failure modes in ICs is based on localized photocurrent generation as disclosed in U.S. Pat. No. 4,698,587 to Burns et al. The method of Burns et al is complicated, requiring that the xe2x80x9cONxe2x80x9d and xe2x80x9cOFFxe2x80x9d states of each transistor being tested be completely mapped during each clock cycle. The information thus obtained must then be stored so that it can be used subsequently to perturb operation of each transistor only during times in which the transistor is transitioning from the xe2x80x9cONxe2x80x9d state to the xe2x80x9cOFFxe2x80x9d state. This perturbation is performed using an above-bandgap focused laser beam which induces a leakage photocurrent in the transistor due to photogenerated carriers (i.e. electrons and holes). This leakage photocurrent slows down switching in the transistor, with the transition time required for the transistor to reach the xe2x80x9cOFFxe2x80x9d state being measured by detecting the induced photocurrent.
What is needed is a method of rapidly measuring functional failures in an IC without the need to first obtain a detailed knowledge of the state of each transistor during each clock cycle. Additionally, a method is needed which allows the identification of circuit elements of whatever type that contribute to timing errors and thereby produce functional failures in an IC. Finally, a method is needed which quickly and directly pinpoints the location of any circuit elements in the IC producing the functional failures without resorting to complicated calculations or analysis.
An advantage of the present invention is that it does not require a detailed knowledge of the state of each transistor in an IC being tested during each clock cycle.
Another advantage of the present invention is that it does not require a photocurrent to be generated in the IC being tested.
A further advantage of the present invention is that it can identify and localize functional failures produced different types of circuit elements, including transistors and resistive interconnections.
Yet another advantage of the present invention is that it can be used to directly and simply form an image or map of the location of any circuit elements in an IC which are responsible for producing functional failures therein.
Still another advantage of the present invention is that it does not measure permanent defects such as open-circuit or short-circuit defects which are unrelated to functional failures and timing errors.
A further advantage of the present invention is that it is nondestructive so that it can be used for qualification testing of ICs without permanently damaging the ICs.
Yet another advantage of the present invention is that it is applicable to the measurement of functional failures in ICs which employ multiple levels of patterned metallization, and to the measurement of functional failures in ICs which are mounted device-side-down in a flip-chip arrangement. The wavelength of a focused laser beam used in the present invention can be selected so that the substrate (e.g. comprising silicon, germanium or a III-V compound semiconductor) whereon the IC is fabricated is sufficiently transmissive to the laser beam so that analysis can be performed through the substrate. This can simplify the analysis since the focused laser beam can access circuit elements (e.g. transistors) of the IC without being blocked by multiple levels of patterned metallization which can overlie the circuit elements.
These and other advantages of the method of the present invention will become evident to those skilled in the art.
The present invention relates to an apparatus for analyzing an IC to identify at least one circuit element responsible for producing a functional failure in the IC. The apparatus comprises means for operating the IC under conditions wherein the functional failure occurs, with the functional failure producing over time a fraction of defective (i.e. incorrect) output states (i.e. output voltages) and a remainder of good output states at one or more outputs from the IC in response to a set of input test vectors repeatedly provided to the IC; a laser producing a beam having a photon energy that is less than a bandgap energy of a substrate (e.g. a silicon substrate) whereon the IC is formed; means for focusing and scanning the laser beam across the IC, thereby producing localized heating within the IC that generates a change in the fraction of defective output states from the IC, the focusing and scanning means further providing a position signal to indicate the location of the laser beam on the IC at any instant in time; and means, receiving inputs of the position signal and the change in the fraction of defective output states from the IC, for mapping the location of each circuit element within the IC responsible for the change in the fraction of defective output states from the IC. The apparatus of the present invention can be used to locate circuit elements such as transistors (e.g. switching transistors) or resistive interconnections that are responsible for producing the functional failures, if any, in an IC being tested.
The means for operating the IC under conditions wherein the functional failure occurs can comprise one or more of the following: a power supply providing an operating voltage to the IC; a temperature-controlled stage for holding the IC and maintaining the IC at a selected temperature; a clock for operating the IC at a selected frequency; means (e.g. an optical filter or electro-optic modulator) for controlling a power level of the laser beam, or means (e.g. a digital IC tester or a computer-controlled switch matrix) for controlling a rate at which the set of input test vectors are repeatedly provided to the IC.
The photon energy of the laser beam is generally selected so that it is insufficient to produce a photocurrent in the IC. In the case of a silicon substrate, the photon energy of the laser beam can be at a wavelength in the range of 1.2 to 2.5 microns, and preferably about 1.3 microns. The laser beam is focused to a spot on the IC to locally heat particular circuit elements in the IC at any instant in time. This can be done, for example, by focusing the laser beam to a micron-sized spot after the laser beam is transmitted-through the substrate.
The means for focusing and scanning the laser beam across the IC comprises at least one lens or curved mirror for focusing the laser to a spot, and further comprises a plurality of moveable mirrors arranged to scan the laser beam in two dimensions. In some embodiments of the present invention, the means for focusing and scanning the laser beam across the IC can comprise a conventional scanning optical microscope (also termed a laser scan microscope).
The mapping means can comprise a display for displaying a map (i.e. an image) to indicate the location of the circuit element in the IC responsible for the change in the fraction of defective output states from the IC. The mapping means can further include an image processor or a computer for accumulating and storing information about the location of the circuit elements in the IC responsible for the change in the fraction of defective output states from the IC. Finally, the mapping means can include a photodetector for detecting a portion of the laser beam reflected or scattered from the IC, with the photodetector providing a detector output signal for generating in combination with the position signal a reflected-light image of the IC being analyzed.
The present invention further relates to an apparatus for analyzing an IC to locate any signal propagation paths that produce timing errors within the IC that result in an incorrect value of an output voltage from the IC. This analysis apparatus comprises means for operating the IC under conditions which produce an incidence (i.e. a rate) of the timing errors in the IC in response to a set of input test vectors provided to the IC; a laser having a beam with a photon energy less than a bandgap energy of a semiconductor substrate whereon the IC is formed; a scanning optical microscope for receiving the laser beam and producing therefrom a focused laser beam which is scanned across a portion of the IC, with the scanning optical microscope further generating a position signal indicative of the position of the focused laser beam at any instant in time, and with the focused laser beam producing localized heating within the IC that changes the incidence of the timing errors in the IC; means connected to the IC for measuring the output voltage from the IC and generating therefrom an analytical output signal whenever the output voltage switches between the incorrect value (i.e. a no-good, defective or faulty value) and a correct value (i.e. a good value); and a display for receiving the position signal and the analytical output signal and generating therefrom a map for locating each signal propagation path within the IC responsible for producing the timing errors.
The means for operating the IC to produce the incidence of timing errors therein can comprise one or more of the following: a stage for heating or cooling the IC; a power supply for providing an operating voltage to the IC; a clock for operating the IC at a selected frequency; means for controlling a power level of the laser beam; or means (e.g. a digital IC tester or a computer-controlled switch matrix) for controlling a rate at which the set of input test vectors are provided to the IC.
The laser beam has a photon energy that is insufficient to produce a photocurrent in the IC. For an IC fabricated on a silicon substrate, the photon energy of the laser beam can be in the range of 1.2-2.5 microns, and preferably about 1.3 microns. An optical filter can be placed in a path of the laser beam, if necessary, to remove any light generated by the laser having a photon energy greater than or equal to the bandgap energy of the semiconductor substrate, thereby preventing the generation of any photocurrents within the IC. Such an optical filter may be necessary, for example, if the laser emits light at a plurality of different wavelengths, including wavelengths corresponding to photon energies above and below the bandgap energy of the substrate. The optical filter can then be used to remove the lasing light from the beam at wavelengths for which the photon energy is above the bandgap energy of the substrate so that no photocurrents are produced.
The scanning optical microscope (also termed a laser scan microscope) comprises at least one lens or curved mirror for focusing the laser beam to a spot, and can further include a photodetector for detecting a portion of the laser beam reflected or scattered from the IC to generate a detector output signal which can be used in combination with the position signal to form a reflected-light image of the IC on the display for superposition with the map to pinpoint the location of each signal propagation path within the IC responsible for producing the timing errors. This can be done even though the laser beam is transmitted through the substrate as is generally required for analyzing ICs mounted in a flip-chip configuration.
The means for measuring the output voltage from the IC and generating the analytical output signal can comprise a latch (e.g. a D-flip-flop) which switches between a pair of logic states therein in response to a change in the output voltage from the IC from the incorrect value to the correct value, or from the correct value to the incorrect value. This allows the apparatus to discriminate between normal (i.e. correct) operation of the IC and abnormal (i.e. incorrect) operation so that only those circuit elements contributing to the timing errors and thereby producing the functional failures in the IC are visualized.
The apparatus can further include an image processor for accumulating a plurality of maps (i.e. images) over time generated from the position signal and the analytical output signal. In this way, the image processor can generate an enhanced-resolution map that can be used to more precisely locate each signal propagation path within the IC responsible for producing the timing errors. A computer can also be used in the apparatus to store information about the location of each signal propagation path producing the timing errors in the IC. Circuit elements which produce timing errors in a signal propagation path can include one or more switching transistors, or one or more resistive interconnections which are defined herein as electrical interconnections having a resistance that is different (i.e. larger or smaller) from the resistance of other similar interconnections in the IC which do not produce timing errors.
Finally, the present invention relates to a method for analyzing an IC and identifying any circuit elements therein responsible for producing functional failures in the IC. The method comprises steps for controlling operational parameters of the IC to induce a level of incidence (i.e. a rate) of the functional failures therein, with the functional failures producing an incorrect value of an output voltage from the IC in response to a set of input test vectors provided to the IC; scanning the IC with a focused laser beam having a photon energy less than a bandgap energy of a substrate whereon the IC is formed to locally heat circuit elements within the IC, thereby changing the level of incidence of the functional failures in the IC; and measuring the change in the level of incidence of the functional failures in the IC as a function of the position of the focused laser beam incident on the IC, thereby locating the circuit elements in the IC responsible for producing the functional failures therein. The method of the present invention can further include a step for forming a map (i.e. an image) of the location of the circuit elements in the IC responsible for producing the functional failures in the IC (e.g. by detecting a portion of the focused laser beam reflected or scattered from the IC), and a step for forming a reflected-light image of the IC for superposition with the map to precisely locate the circuit elements in the IC responsible for producing the functional failures.
The step for controlling operational parameters of the IC to induce the level of incidence of the functional failures therein can comprise controlling a voltage for powering the IC, controlling the temperature of the IC, controlling a clock frequency provided to the IC, controlling a rate at which the set of input test vectors is provided to the IC, controlling a power level of the focused laser beam, or a combination thereof.
When the substrate comprises silicon, the step for scanning the IC with the focused laser beam can comprise scanning the IC with a focused laser beam having a wavelength in the range of 1.2 to 2.5 microns, and preferably about 1.3 microns. The step for scanning the IC with the focused laser beam can further comprise scanning the IC from a backside of a substrate whereon the IC is formed, with the focused laser beam being transmitted through the substrate. Finally, the step for scanning the IC with the focused laser beam can include generating a position signal for indicating the location of the focused laser beam on the IC at any instant in time.
The step for measuring the change in the level of incidence of the functional failures in the IC as a function of the position of the focused laser beam incident on the IC can comprise comparing the value of the output voltage from the IC at each clock cycle and detecting a change in the value of the output voltage from the IC. Additionally, a step can be provided for generating an analytical output signal having an intensity that depends upon the value of the output voltage from the IC, with the analytical output signal being in a first state when the output voltage from the IC has an incorrect value, and with the analytical output, signal being in a second state when the output voltage from the IC has a correct value. Furthermore, the step for measuring the change in the level of incidence of the functional failures in the IC as a function of the position of the focused laser beam incident on the IC can comprise repeatedly scanning the IC with the focused laser beam and accumulating changes in the level of incidence of the functional failures in the IC over time. This can be used to improve a level of detectability of the circuit elements in the IC responsible for producing the functional failures in the IC.
Additional advantages and novel features of the invention will become apparent to those skilled in the art upon examination of the following detailed description thereof when considered in conjunction with the accompanying drawings. The advantages of the invention can be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.